A typical flash memory includes a memory array having a large number of memory cells arranged in blocks. Each of the memory cells includes a field effect transistor having a control gate and a floating gate. The floating gate holds a charge and is separated from source and drain regions in a substrate by a layer of thin oxide. Each memory cell can be electrically charged by electrons injected onto the floating gate. The charge may be removed from the floating gate by tunneling to the source region or an erase gate during an erase operation. The data in flash memory cells are thus determined by the presence or absence of charge in the floating gates.
A conventional flash memory structure is substantially vertical. Spacers of specified thickness are sometimes formed between the word line and the floating gate and between the erase line and the floating gate to reduce leakage current and prevent mass program function failure. However, increasing the thickness of such spacers may also undesirably decrease the erase speed of the memory cells and increase the size of the overall memory cell structure.
There is therefore a need for a flash memory structure with reduced leakage current while maintaining a desirable erase speed. This need increases as fabrication process feature sizes decreases.